1. Field of the Invention
The present invention relates to a chip package, and more particularly, to an improved bottom lead semiconductor package (BLP) and a fabrication method thereof.
2. Background of the Related Art
Among generally known semiconductor chip packages, there are a small outline package (SOP) and a small outline J-lead (SOJ) in which the outer leads serving as electrical connection paths are exposed through sides of the package body. In such conventional semiconductor packages as described above, an area occupied by the package on a printed circuit board becomes increased mainly due to outer leads being protruded through sides of the package body during a mounting operation, thereby further generating quality problems during operation and transporting thereof.
FIG. 1 illustrates a schematic cross-sectional view of a conventional bottom lead semiconductor package mounted on a printed circuit board. Such a package is disclosed in U.S. Pat. No. 5,428,248 (issued Jun. 27, 1995) entitled "Bottom Lead Semiconductor Package (BLP)," which solves the above-described problems, and commonly assigned to the same assignee of the present invention. The package includes a lead frame 13 including a plurality of bottom leads 11. A bottom surface of each of the leads 11 are in contact with the printed circuit board 20. A plurality of inner leads 12 is respectively bent upwardly extending from a corresponding one of the bottom leads 11.
A semiconductor chip 15 is attached to an upper surface of each of the bottom leads 11 by adhesives 14, and a plurality of conductive wires 16 electrically connects chip pads (not shown) of the chip 15 to the inner leads 12 of the lead frame 13. A molding resin molds the wires 16, the semiconductor chip 15 and the respective leads 11, 12 of the lead frame 13 to form a package body 17. At this time, a portion of each of the bottom leads 11 is exposed through a bottom surface of the package body 17, and then the exposed lower surfaces of bottom leads 11 are plated with lead (not shown).
The bottom lead semiconductor package decreases a substrate-occupancy area and eliminates the outer leads which might become damaged. However, when the package is mounted on printed circuit board 20 by forming a solder 25 on a lower surface of each of the bottom leads 11, there is a solder joint (an electrical contact provided between a bottom lead and the printed circuit board by a solder) reliability problem because the lower surfaces of the bottom leads 11 and the bottom surface of the package body 17 are formed almost flush with each other due to the solder 25. Further, the package mounted on the printed circuit board can be unnecessarily raised by as much as the height of the solder 25.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.